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SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
March 1993 Revised August 2000
SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
General Description
The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANPSC110F Bridge supports up to 3 local scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.
Features
s True IEEE1149.1 hierarchical and multidrop addressable capability s The 6 slot inputs support up to 59 unique addresses, a Broadcast Address, and 4 Multi-cast Group Addresses s 3 IEEE 1149.1-compatible configurable local scan ports s Mode Register allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three s 32-bit TCK counter s 16-bit LFSR Signature Compactor s L4 s local TAPs can be 3-stated via the OE input to allow an alternate test master to take control of the local TAPs
Ordering Code:
Order Number SCANPSC110FSC Package Number M28B Package Description 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names TCKB TMSB TDIB TDOB TRST S(0,5) OE Description Backplane Test Clock Input Backplane Test Mode Select Input Backplane Test Data Input Backplane Test Data Output Asynchronous Test Reset Input (Active LOW) Address Select Port Local Scan Port Output Enable (Active LOW)
TCKL(1-3) Local Port Test Clock Output TMSL(1-3) Local Port Test Mode Select Output TDIL(1-3) Local Port Test Data Input TDOL(1-3) Local Port Test Data Output
(c) 2000 Fairchild Semiconductor Corporation
DS011570
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SCANPSC110F
TABLE 1. Glossary of Terms LFSR LSP Local Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial test data. Local Scan Port. A four signal port that drives a "local" (i.e. non-backplane) scan chain. (e.g., TCKL1, TMSL1, TDOL1, TDIL1) Local is used to describe IEEE Std. 1149.1 compliant scan rings and the SCANPSC110F Bridge Test Access Port that drives them. The term "local" was adopted from the system test architecture that the SCANPSC110F Bridge will most commonly be used in; namely, a system test backplane with a SCANPSC110F Bridge on each card driving up to 3 "local" scan rings per card. (Each card can contain multiple SCANPSC110Fs, with 3 local scan ports per SCANPSC110F.) Park, parked, unpark, and unparked, are used to describe the state of the LSP controller and the state of the local TAP controllers (the "local TAP controllers" refers to the TAP controllers of the scan components that make up a local scan ring). Park is also used to describe the action of parking a LSP (transitioning into one of the Parked LSP controller states). It is important to understand that when a LSP controller is in one of the parked states, TMSL is held constant, thereby holding or "parking" the local TAP controllers in a given state. Test Access Port as defined by IEEE Std. 1149.1
Park/Unpark
TAP
Selected/Unselected Selected and Unselected refers to the state of the SCANPSC110F Bridge Selection Controller. A selected SCANPSC110F has been properly addressed and is ready to receive Level 2 protocol. Unselected SCANPSC110Fs monitor the system test backplane, but do not accept Level 2 protocol (except for the GOTOWAIT instruction). The data registers and LSPs of unselected SCANPSC110Fs are not accessible from the system test master. Active Scan Chain The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given moment. When a SCANPSC110F is selected with all of its LSPs parked, the active scan chain is the current scan bridge register only. When a LSP is unparked, the active scan chain becomes: TDIB the current SCANPSC110F register the local scan ring registers a PAD bit TDOB. Refer to Table 4 for Unparked configurations of the LSP network. Level 1 is the protocol used to address a SCANPSC110F. Level 2 is the protocol that is used once a SCANPSC110F is selected. Level 2 protocol is IEEE Std. 1149.1 compliant when an individual SCANPSC110F is selected. A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates the prop delay that would be added by the SCANPSC110F LSPN logic between TDILn and TDOL(n+1) or TDOB by buffering and synchronizing the TDIL inputs to the falling edge of TCKB, thus allowing data to be scanned at higher frequencies without violating set-up and hold times. Least Significant Bit, the right-most position in a register (bit 0) Most Significant Bit, the left-most position in a register
Level 1 Protocol Level 2 Protocol PAD
LSB MSB
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SCANPSC110F
TABLE 2. Detailed Pin Description Table Name TMSB I/O (Note 1) TTL Input w/Pull-Up Resistor Pin # (SOIC & LCC) 10 Description BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the SCANPSC110F Bridge. Also controls sequencing of the TAPs which are on the three (3) local scan chains. BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the SCANPSC110F through this input pin. BACKPLANE TEST DATA OUTPUT: This output drives test data from the SCANPSC110F and the local TAPs, back toward the scan master controller.
TDIB TDOB
TTL Input w/Pull-Up Resistor 3-STATEable, 32 mA/64 mA Drive, Reduced-Swing, Output
12 13
TCKB
TTL Schmitt Trigger Input
11
TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls all scan operations of the SCANPSC110F and of the three (3) local scan ports. TEST RESET: An asynchronous reset signal (active LOW) which initializes the SCANPSC110F logic. SLOT IDENTIFICATION: The configuration of these six (6) pins is used to identify (assign a unique address to) each SCANPSC110F on the system backplane. OUTPUT ENABLE for the Local Scan Ports, active LOW. When HIGH, this active-LOW control signal 3-STATEs all three local scan ports on the SCANPSC110F, to enable an alternate resource to access one or more of the three (3) local scan chains. TEST DATA OUTPUTS: Individual output for each of the three (3) local scan ports.
TRST S(0-5)
TTL Input w/Pull-Up Resistor TTL Inputs
9 2, 3, 4, 5, 6, 7
OE
TTL Input
1
TDOL(1-3) 3-STATEable, 24 mA/24 mA Drive Outputs TDIL(1-3) TTL Inputs w/Pull-Up Resistors TMSL(1-3) 3-STATEable, 24 mA/24 mA Drive Outputs TCKL(1-3) 3-STATEable, 24 mA/24 mA Drive Output VCC GND Power Supply Voltage Ground potential
15,19, 24 18, 23, 27 16, 20, 25
TEST DATA INPUTS: Individual scan data input for each of the three (3) local scan ports. TEST MODE SELECT OUTPUTS: Individual output for each of the three (3) local scan ports. TMSL does not provide a pull-up resistor (which is assumed to be present on a connected TMS input, per the IEEE 1149.1 requirement) LOCAL TEST CLOCK OUTPUTS: Individual output for each of the three (3) local scan ports. These are buffered versions of TCKB. Power supply pins, 5.0V 10%. Power supply pins 0V.
17, 22, 26 8, 28 14, 21
Note 1: All pins are active HIGH unless otherwise noted.
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SCANPSC110F
Overview of SCANPSC110F Bridge Functions
FIGURE 1. SCANPSC110F Bridge Architecture SCANPSC110F BRIDGE ARCHITECTURE Figure 1 shows the basic architecture of the SCANPSC110F. The device's major functional blocks are illustrated here. The TAP Controller, a 16-state state machine, is the central control for the device. The instruction register and various test data registers can be scanned to exercise the various functions of the SCANPSC110F (these registers behave as defined in IEEE Std. 1149.1). The SCANPSC110F selection controller provides the functionality that allows the 1149.1 protocol to be used in a multi-drop environment. It primarily compares the address input to the slot identification and enables the SCANPSC110F for subsequent scan operations. The Local Scan Port Network (LSPN) contains multiplexing logic used to select different port configurations. The LSPN control block contains the Local Scan Port Controllers (LSPC) for each Local Scan Port (LSP1, LSP2, and LSP3). This control block receives input from the SCANPSC110F instruction register, mode register, and the TAP controller. Each local port contains all four (4) boundary scan signals needed to interface with the local TAPs. SCANPSC110F BRIDGE STATE MACHINES The SCANPSC110F is IEEE 1149.1-compatible, in that it supports all required 1149.1 operations. In addition, it supports a higher level of protocol, (Level 1), that extends the IEEE 1149.1 Std. to a multi-drop environment. In multi-drop scan systems, a scan tester can select individual SCANPSC110Fs for participation in upcoming scan operations. SCANPSC110F "selection" is accomplished by simultaneously scanning a device address out to multiple SCANPSC110Fs. Through an on-chip address matching process, only those SCANPSC110Fs whose staticallyassigned address matches the scanned-out address become selected to receive further instructions from the scan tester. SCANPSC110F selection is done using a "Level-1" protocol, while follow-on instructions are sent to selected SCANPSC110Fs by using a "Level-2" protocol.
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SCANPSC110F
Overview of SCANPSC110F Bridge Functions
(Continued)
The SCANPSC110F contains three distinct but coupled state-machines (see Figure 2). The first of these is the TAP-control state-machine, which is used to drive the SCANPSC110Fs scan ports in conformance with the 1149.1 Standard (see Figure 17 of appendix). The second is the SCANPSC110F-selection state-machine (Figure 3). The third state-machine actually consists of three identical but independent state-machines (see Figure 4), one per SCANPSC110F local scan port. Each of these scan portselection state-machines allows individual local ports to be
FIGURE 2. SCANPSC110F Bridge State Machines inserted into and removed from the SCANPSC110Fs overall scan chain. The SCANPSC110F selection state-machine performs the address matching which gives the SCANPSC110F its multi-drop capability. That logic supports singleSCANPSC110F access, multi-cast, and broadcast. The SCANPSC110F-selection state-machine implements the chip's Level-1 protocol.
KEY + = OR & = AND ADDR = 6-bit address in the Instruction Register SLOT = Static address in the SCANPSC110F Selection Controller
FIGURE 3. State Machine for SCANPSC110F Bridge Selection Controller
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SCANPSC110F
Overview of SCANPSC110F Bridge Functions
(Continued)
The SCANPSC110F's scan port-configuration statemachine is used to control the insertion of local scan ports into the overall scan chain, or the isolation of local ports from the chain. From the perspective of a system's (single) scan controller, each SCANPSC110F presents only one scan chain to the master. The SCANPSC110F architecture allows one or more of the SCANPSC110F's local ports to be included in the active scan chain.
FIGURE 4. Local SCANPSC110F Bridge Port Configuration State Machine enters the Parked-RTI state in which TMSLn will be held LOW until the port is later unparked. While TMSLn is held LOW, all devices on that local scan chain remain in their current TAP State (the RTI TAP controller state in this example). The SCANPSC110F's scan port-configuration statemachine implements part of the SCANPSC110F's Level-2 protocol. In addition, the SCANPSC110F provides a number of Level-2 instructions for functions other than local scan port configuration. These instructions provide access to and control of various registers within the SCANPSC110F. This set instructions includes: BYPASS EXTEST SAMPLE/PRELOAD IDCODE MODESEL MCGRSEL LFSRSEL Figure 5 illustrates how the SCANPSC110F's statemachines interact. The SCANPSC110F-selection statemachine enables or disables operation of the chip's three port-selection state-machines. In SCANPSC110Fs which are selected via Level-1 protocol (either as individual SCANPSC110Fs or as members of broadcast or multi-cast groups), Level-2 protocol commands can be used to park or unpark local scan ports. Note that most transitions of the port-configuration state-machines are gated by particular states of the SCANPSC110F's TAP-control state-machine, as shown in Figures 4, 5. CNTRSEL LFSRON LFSROFF CNTRON CNTROFF GOTOWAIT
Each local port can be "parked" in one of four stable states (Parked-TLR, Parked-RTI, Parked-Pause-DR or ParkedPause-IR), either individually or simultaneously with other local ports. Parking a chain removes that local chain from the active scan chain. Conversely, a parked chain can be "unparked", causing the corresponding local port to be inserted into the active scan chain. As shown in Figure 4, the SCANPSC110F's three scan port-configuration state-machines allow each of the part's local ports to occupy a different state at any given time. For example, some ports may be parked, perhaps in different states, while other ports participate in scan operations. The state-diagram shows that some state transitions depend on the current state of the TAP-control state-machine. As an example, a local port which is presently in the Parked-RTI state does not become unparked (i.e., enter the Unparked state) until the SCANPSC110F receives an UNPARK instruction and the SCANPSC110F's TAP state-machine enters the Run-Test/Idle state. Similarly, certain transitions of the scan port-configuration state-machine can force the SCANPSC110F's TAP-control state-machine into specific states. For example, when a local port is in the Unparked state and the SCANPSC110F receives a PARKRTI instruction, the Local Port controller
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SCANPSC110F
Overview of SCANPSC110F Bridge Functions
(Continued)
FIGURE 5. Relationship Between SCANPSC110F Bridge State Machines Following a hardware reset, the TAP controller statemachine is in the Test-Logic-Reset (TLR) state; the SCANPSC110F-selection state-machine is in the Wait-ForAddress state; and each of the three port-selection statemachines is in the Parked-TLR state. The SCANPSC110F is then ready to receive Level-1 protocol, followed by Level2 protocol. When the instruction register is updated with the address data, the SCANPSC110F's address-recognition logic compares the six least-significant bits of the instruction register with the 6-bit assigned address which is statically present on the S(0-5) inputs. Simultaneously, the scanned-in address is compared with the reserved Broadcast and Multi-cast addresses. If an address match is detected, the SCANPSC110F-selection state-machine enters one of the two selected states. If the scanned address does not match a valid single-slot address or one of the reserved broadcast/multi-cast addresses, the SCANPSC110F-selection state-machine enters the Unselected state. Note that the SLOT inputs should not be set to a value corresponding to a multi-cast group, or to the broadcast address. Also note that the single-SCANPSC110F selection process must be performed for all SCANPSC110Fs which are subsequently to be addressed in multi-cast mode. This is required because each such device's Multicast Group Register (MCGR) must be programmed with a multi-cast group number, and the MCGR is not accessible to the test controller until that SCANPSC110F has first entered the Selected-Single-SCANPSC110F state. Once a SCANPSC110F has been selected, Level-2 protocol is used to issue commands and to access the chip's various registers. 7 www.fairchildsemi.com
Tester/SCANPSC110F Bridge Interface
An IEEE 1149.1 system tester sends instructions to a SCANPSC110F via that SCANPSC110F's backplane scanport. Following test logic reset, the SCANPSC110F's selection state-machine is in the Wait-For-Address state. When the SCANPSC110F's TAP controller is sequenced to the Shift-IR state, data shifted in through the TDIB input is shifted into the SCANPSC110F's instruction register. Note that prior to successful selection of a SCANPSC110F, data is not shifted out of the instruction register and out through the SCANPSC110F's TDOBoutput, as it is during normal scan operations. Instead, as each new bit enters the instruction register's most-significant bit, data shifted out from the least-significant bit is discarded.
SCANPSC110F
Tester/SCANPSC110FBridge Interface Register Set
The SCANPSC110F Bridge includes a number of registers which are used for SCANPSC110F selection and configuration, scan data manipulation, and scan-support operations. These registers can be grouped as shown in Table 3. The specific fields and functions of each of these registers are detailed in the section of this document titled "Data Register Descriptions".
(Continued)
Note that when any of these registers is selected for insertion into the SCANPSC110F's scan-chain, scan data enters through that register's most-significant bit. Similarly, data that is shifted out of the register is fed to the scan input of the next-downstream device in the scan-chain.
TABLE 3. Registers Register Name Instruction Register Boundary-Scan Register Bypass Register Device Identification Register Multi-Cast Group Register Mode Register Linear-Feedback Shift Register TCK Counter Register BSDL Name INSTRUCTION BOUNDARY BYPASS IDCODE MCGR MODE LFSR CNTR Description SCANPSC110F addressing and instruction-decode IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 optional register SCANPSC110F-group address assignment SCANPSC110F local-port configuration and control bits SCANPSC110F scan-data compaction (signature generation) Local-port TCK clock-gating (for BIST)
Addressing Scheme
The SCANPSC110F Bridge architecture extends the functionality of the IEEE 1149.1 Standard by supplementing that protocol with an addressing scheme which allows a test controller to communicate with specific SCANPSC110Fs within a network of SCANPSC110Fs. That network can include both multi-drop and hierarchical connectivity. In effect, the SCANPSC110F architecture allows a test controller to dynamically select specific portions of such a network for participation in scan operations. This allows a complex system to be partitioned into smaller blocks for testing purposes. The SCANPSC110F provides two levels of test-network partitioning capability. First, a test controller can select entire individual SCANPSC110Fs, specific sets of SCANPSC110Fs (multi-cast groups), or all SCANPSC110Fs (broadcast). This SCANPSC110F-selection process is supported by a "Level-1" communication protocol. Second, within each selected SCANPSC110F, a test controller can select one or more of the chip's three local scan-ports. That is, individual local ports can be selected for inclusion in the (single) scan-chain which a SCANPSC110F presents to the test controller. This mechanism allows a controller to select specific terminal scanchains within the overall scan network. The port-selection process is supported by a "Level-2" protocol.
Hierarchical Test Support
Multiple SCANPSC110F Bridges can be used to assemble a hierarchical boundary-scan tree. In such a configuration, the system tester can configure the local ports of a set of SCANPSC110Fs so as to connect a specific set of local scan-chains to the active scan chain. Using this capability, the tester can selectively communicate with specific portions of a target system. The tester's scan port is connected to the backplane scan port of a "root" layer of SCANPSC110Fs, each of which can be selected using multi-drop addressing. A second tier of SCANPSC110Fs can be connected to this root layer, by connecting a local port (LSP) of a root-layer SCANPSC110F to the backplane port of a second-tier SCANPSC110F. This process can be continued to construct a multi-level scan hierarchy. SCANPSC110F local ports which are not cascaded into higher-level SCANPSC110Fs can be thought of as the terminal "leaves" of a scan "tree". The test master can select one or more target leaves by selecting and configuring the local ports of an appropriate set of SCANPSC110Fs in the test tree.
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SCANPSC110F
Level 1 Protocol
ADDRESSING MODES The SCANPSC110F Bridge supports "single" and "multiple" modes of addressing a SCANPSC110F. The "single" mode will select one SCANPSC110F and is called Direct Addressing. More than one SCANPSC110F device can be selected via the Broadcast and Multi-Cast Addressing modes.
TABLE 4. SCANPSC110F Bridge Address Modes Address Types Direct Address Broadcast Address Multi-Cast Group 0 Multi-Cast Group 1 Multi-Cast Group 2 Multi-Cast Group 3 Hex Address (Note 2) 00 to 3A 3B 3C 3D 3E 3F Binary Address (Note 3) XX000000 to XX111010 XX111011 XX111100 XX111101 XX111110 XX111111 TDOB State Normal IEEE Std. 1149.1 Always 3-STATED Always 3-STATED Always 3-STATED Always 3-STATED Always 3-STATED
Note 2: Hex address '7X', 'BX', or 'FX' may be used instead of '3X'. Note 3: Only the six (6) LSB's of the address is compared to the S(0-5) inputs. The two (2) MSB's are "don't cares".
DIRECT ADDRESSING The SCANPSC110F enters the Wait-For-Address state when: 1. its TAP Controller enters the Test-Logic-Reset state, or 2. its instruction register is updated with the GOTOWAIT instruction (while either selected or unselected). Each SCANPSC110F within a scan network must be statically configured with a unique address via its S(0-5) inputs. While the SCANPSC110F controller is in the Wait-ForAddress state, data shifted into bits 5 through 0 of the instruction register is compared with the address present on the S(0-5)inputs in the Update-IR state. If the six (6) LSBs of the instruction register match the address on the S(0-5) inputs, (see Figure 6) the SCANPSC110F becomes selected, and is ready to receive Level 2 Protocol (i.e., further instructions). When the SCANPSC110F is selected, its device identification register is inserted into the active scan chain. All SCANPSC110Fs whose S(0-5) address does not match the instruction register address become unselected. They will remain unselected until either their TAP Controller enters the Test-Logic-Reset state, or their instruction register is updated with the GOTOWAIT instruction.
FIGURE 6. Direct Addressing: Device Address Loaded into Instruction Register BROADCAST ADDRESSING The Broadcast Address allows a tester to simultaneously select all SCANPSC110Fs in a test network. This mode is useful in testing systems which contain multiple identical boards. To avoid bus contention between scan-path output drivers on different boards, each SCANPSC110F's TDOB buffer is always 3-stated while in Broadcast mode. In this configuration, the on-chip Linear Feedback Shift Register (LFSR) can be used to accumulate a test result signature for each board that can be read back later by directaddressing each board's SCANPSC110F. MULTI-CAST ADDRESSING As a way to make the broadcast mechanism more selective, the SCANPSC110F provides a "Multi-cast" addressing mode. A SCANPSC110F's multi-cast group register (MCGR) can be programmed to assign that SCANPSC110F to one of four (4) Multi-Cast groups. When SCANPSC110Fs in the Wait-For-Address state are updated with a Multi-Cast address, all SCANPSC110Fs whose MCGR matches the Multi-Cast group will become selected. As in Broadcast mode, TDOB is always 3-stated while in Multi-cast mode.
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SCANPSC110F
Level 1 Protocol
(Continued)
FIGURE 7. Broadcast Addressing: Address Loaded into Instruction Register
FIGURE 8. Multi-Cast Addressing: Address Loaded into Instruction Register
Level 2 Protocol
Once the SCANPSC110F Bridge has been successfully addressed and selected, its internal registers may be accessed via Level-2 Protocol. Level-2 Protocol is compliant to IEEE Std. 1149.1 TAP protocol with one exception: if the SCANPSC110F is selected via the Broadcast or MultiCast address, TDOB will always be 3-STATED. (The TDOB buffer must be implemented this way to prevent bus contention.) Upon being selected, (i.e., the SCANPSC110F Selection controller transitions from the Wait-For-Address state to one of the Selected states), each of the local scan ports (LSP1, LSP2, LSP3) remains parked in one of the following four TAP Controller states: Test-Logic-Reset, Run-Test/ Idle, Pause-DR, or Pause-IR and the active scan chain will consist of: TDIB through the instruction register (or the IDCODE register) and out through TDOB. TDIBInstruction RegisterTDOB www.fairchildsemi.com 10 The UNPARK instruction (described later) is used to insert one or more local scan ports into the active scan chain. Table 4 describes which local ports are inserted into the chain, and in what order. LEVEL 2 INSTRUCTION TYPES There are two types of instructions (reference Table 5): 1. Instructions that insert a SCANPSC110F register into the active scan chain so that the register can be captured or updated (BYPASS, SAMPLE/PRELOAD, EXTEST, IDCODE, MODESEL, MCGRSEL, LFSRSEL, CNTRSEL). 2. Instructions that configure local ports or control the operation of the linear feedback shift register and counter registers (UNPARK, PARKTRL, PARKRTI, PARKPAUSE, GOTOWAIT, SOFTRESET, LFSRON, LFSROFF, CNTRON, CNTROFF). These instructions,
SCANPSC110F
Level 2 Protocol
(Continued) along with any other yet undefined Op-Codes, will cause the device identification register to be inserted into the active scan chain.
same function as the SAMPLE/PRELOAD instruction, since there aren't any scannable outputs on the device. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction selects the boundary-scan register for insertion into the active scan chain. The boundary-scan register consists of seven "sample only" shift cells connected to the S(0-5) and OE inputs. IDCODE: The IDCODE instruction selects the device identification register for insertion into the active scan chain. When IDCODE is the current active instruction the device identification "0FC0E01F" Hex is captured upon exiting the Capture-DR state.
LEVEL 2 INSTRUCTION DESCRIPTIONS BYPASS: The BYPASS instruction selects the bypass register for insertion into the active scan chain when the SCANPSC110F is selected. EXTEST: The EXTEST instruction selects the boundaryscan register for insertion into the active scan chain. The boundary-scan register consists of seven "sample only" shift cells connected to the S(0-5) and OE inputs. On the SCANPSC110F, the EXTEST instruction performs the
TABLE 5. Level 2 Protocol and Op-Codes Instructions BYPASS EXTEST SAMPLE/PRELOAD IDCODE UNPARK PARKTLR PARKRTI PARKPAUSE GOTOWAIT* MODESEL MCGRSEL SOFTRESET LFSRSEL LFSRON LFSROFF CNTRSEL CNTRON CNTROFF Other Undefined Hex Op-Code FF 00 81 AA E7 C5 84 C6 C3 8E 03 88 C9 0C 8D CE 0F 90 TBD Binary Op-Code 11111111 00000000 10000001 10101010 11100111 11000101 10000100 11000110 11000011 10001110 00000011 10001000 11001001 00001100 10001101 11001110 00001111 10010000 TBD Data Register Bypass Register Boundary-Scan Register Boundary-Scan Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Mode Register Multi-Cast Group Register Device Identification Register Linear Feedback Shift Register Device Identification Register Device Identification Register 32-Bit TCK Counter Register Device Identification Register Device Identification Register Device Identification Register
Note 4: All other instructions act on selected SCANPSC110Fs only.
UNPARK: This instruction unparks the Local Scan Port Network and inserts it into the active scan chain as configured by the Mode register (see Table 4). Unparked LSPs are sequenced synchronously with the SCANPSC110F's TAP controller. When a LSP has been parked in the Test-Logic-Reset or Run-Test/Idle state, it will not become unparked until the SCANPSC110F's TAP Controller enters the Run-Test/Idle state following the UNPARK instruction. If an LSP has been parked in one of the stable pause states (Pause-DR or Pause-IR), it will not become unparked until the SCANPSC110F's TAP Controller enters the respective pause state. (See Figures 9, 10, 11, 12). PARKTLR: This instruction causes all unparked LSPs to be parked in the Test-Logic-Reset TAP controller state and removes the LSP network from the active scan chain. The LSP controllers keep the LSPs parked in the Test-LogicReset state by forcing their respective TMSL output with a constant logic "1" while the LSP controller is in the ParkedTLR state (see Figure 4). PARKRTI: This instruction causes all unparked LSPs to be parked in the Run-Test/Idle state. When a LSPn is active 11
(unparked), its TMSL signals follow TMSB and the LSPn controller state transitions are synchronized with the TAP Controller state transitions of the SCANPSC110F. When the instruction register is updated with the PARKRTI instruction, TMSLwill be forced to a constant logic "0", causing the unparked local TAP Controllers to be parked in the Run-Test/Idle state. When an LSPn is parked, it is removed from the active scan chain. PARKPAUSE: The PARKPAUSE instruction has dual functionality. It can be used to park unparked LSPs or to unpark parked LSPs. The instruction places all unparked LSPs in one of the TAP Controller pause states. A local port does not become parked until the SCANPSC110F's TAP Controller is sequenced through Exit1-DR/IR into the UpdateDR/IR state. When the SCANPSC110F TAP Controller is in the Exit1-DR or Exit1-IR state and TMSB is HIGH, the LSP controller forces a constant logic '0" onto TMSL thereby parking the port in the Pause-DR or Pause-IR state respectively (see Figure 4 ). Another instruction can then be loaded to reconfigure the local ports or to deselect the SCANPSC110F (i.e., MODESEL, GOTOWAIT, etc.).
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SCANPSC110F
Level 2 Protocol
(Continued) If the PARKPAUSE instruction is given to a bridge whose LSPs are parked in Pause-IR or Pause-DR, the parked LSPs will become unparked when the SCANPSC110F's TAP controller is sequenced into the respective Pause state. The PARKPAUSE instruction was implemented with this dual functionality to enable backplane testing (interconnect testing between boards) with simultaneous Updates and Captures.
LFSRSEL: This instruction inserts the linear feedback shift register (LFSR) into the active scan chain, allowing a compacted signature to be shifted out of the LFSR during the Shift-DR state. (The signature is assumed to have been computed during earlier LFSRON shift operations.) This instruction disables the LFSR register's feedback circuitry, turning the LFSR into a standard 16-bit shift register. This allows a signature to be shifted out of the register, or a seed value to be shifted into it. LFSRON: Once this instruction is executed, the linear feedback shift register samples data from the active scan path (including all unparked TDILn) during the Shift-DR state. Data from the scan path is shifted into the linear feedback shift register and compacted. This allows a serial stream of data to be compressed into a 16-bit signature that can subsequently be shifted out using the LFSRSEL instruction. The linear feedback shift register is not placed in the scan chain during this mode. Instead, the register samples the active scan-chain data as it flows from the LSPN to TDOB. LFSROFF: This instruction terminates linear feedback shift register sampling. The LFSR retains its current state after receiving this instruction. CNTRSEL: This instruction inserts the 32-bit TCK counter shift register into the active scan chain. This allows the user to program the number of "n" TCK cycles to send to the parked local ports once the CNTRON instruction is issued (e.g., for BIST operations). Note that to ensure completion of count-down, the SCANPSC110F should receive at least "n" TCKB pulses. CNTRON: This instruction enables the TCK counter. The counter begins counting down on the first rising edge of TCKB following the Update-IRTAP controller state and is decremented on each rising edge of TCKB thereafter. When the TCK counter reaches terminal count, "00000000" Hex, TCKL of all parked LSP's is held LOW. The CNTROFF instruction must be issued before unparking the LSPs of a SCANPSC110F whose counter has reached terminal count. This function over-rides the mode register TCK control bit (bit-3). CNTROFF: This instruction disables the TCK counter, and TCKL control is returned to the mode register (bit-3).
Simultaneous Update and Capture of several boards can be performed by parking LSPs of the different boards in the Pause-DR TAP controller state, after shifting the data to be updated into the boundary registers of the components on each board. The broadcast address is used to select all SCANPSC110Fs connected to the backplane. The PARKPAUSE instruction is scanned into the selected SCANPSC110Fs and the SCANPSC110F TAP controllers are sequenced to the Pause-DR state where the LSPs of all SCANPSC110Fs become unparked. The local TAP controllers are then sequenced through the Update-DR, Select-DR, Capture-DR, Exit1-DR, and parked in the Pause-DR state, as the SCANPSC110F TAP controller is sequenced into the Update-DR state. When a LSP is parked, it is removed from the active scan chain. GOTOWAIT: This instruction is used to return all SCANPSC110Fs to the Wait-For-Address state. All unparked LSPs will be parked in the Test-Logic-Reset TAP controller state (see Figure 5). MODESEL: The MODESEL instruction inserts the mode register into the active scan chain. The mode register determines the LSPN configuration. Bit 7 of the mode register is a read-only counter status flag. MCGRSEL: This instruction inserts the multi-cast group register (MCGR) into the active scan chain. The MCGR is used to group SCANPSC110Fs into multi-cast groups for parallel TAP sequencing (i.e., to simultaneously perform identical scan operations). SOFTRESET: This instruction causes all 3 Port configuration controllers (Figure 4) to enter the Parked-TLR state, which forces TMSLn HIGH; this parks each local port in the Test-Logic-Reset state within 5 TCKBcycles.
FIGURE 9. Local Scan Port Synchronization from Parked-TLR Instruction
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SCANPSC110F
Level 2 Protocol
(Continued)
FIGURE 10. Local Scan Port Synchronization from Parked-RTI State
Register Descriptions
Instruction Register The instruction shift register is an 8-bit register that is in series with the scan chain whenever the TAP Controller of the SCANPSC110F Bridge is in the Shift-IR state. Upon exiting the Capture-IR state, the value "XXXXXX01" is captured into the instruction register, where "XXXXXX" represents the value on the S(0-5) inputs. When the SCANPSC110F controller is in the Wait-ForAddress state, the instruction register is used for SCANPSC110F selection via address matching. In addressing individual SCANPSC110Fs, the chip's addressing logic performs a comparison between a statically-configured (hard-wired) value on that SCANPSC110F's slot inputs, and an address which is scanned into the chip's instruction register. Binary address codes "000000" through "111010" ("00" through "3A" Hex) are reserved for addressing individual SCANPSC110Fs. Address "3B" Hex is for Broadcast mode. In doing multi-cast (group) addressing, a scanned-in address is compared against the (previously scanned-in) contents of a SCANPSC110F's Multi-Cast Group register. Binary address codes "111110" through "111111" ("3A" through "3F" Hex) are reserved for multi-cast addressing, and should not be assigned as SCANPSC110F slot-input values. Boundary-Scan Register The boundary-scan register is a "sample only" shift register containing cells from the S(0-5) and OE inputs. The register allows testing of circuitry external to the SCANPSC110F. It permits the signals flowing between the system pins to be sampled and examined without interfering with the operation of the on-chip system logic. The scan chain is arranged as follows: TDIBOE S5S4 S3 S2S1S0LSPNTDOB Bypass Register The bypass register is a 1-bit register that operates as specified in IEEE Std. 1149.1 once the SCANPSC110F has been selected. The register provides a minimum length serial path for the movement of test data between TDIB and the LSPN. This path can be selected when no other test data register needs to be accessed during a boardlevel test operation. Use of the bypass register shortens the serial access-path to test data registers located in other components on a board-level test data path. Multi-Cast Group Register "Multi-cast" is a method of simultaneously communicating with more than one selected SCANPSC110F. The multi-cast group register (MCGR) is a 2-bit register used to determine which multi-cast group a particular SCANPSC110F is assigned to. Four addresses are reserved for multi-cast addressing. When a SCANPSC110F is in the Wait-For-Address state and receives a multi-cast address, and if that SCANPSC110F's MCGR contains a matching value for that multi-cast address, the SCANPSC110F becomes selected and is ready to receive Level 2 Protocol (i.e., further instructions). The MCGR is initialized to "00" upon entering the TestLogic-Reset state. The following actions are used to perform multi-cast addressing: 1. Assign all target SCANPSC110Fs to a multi-cast group by writing each individual target SCANPSC110F's MCGR with the same multi-cast group code (see Table 6). This configuration step must be done by individually addressing each target SCANPSC110F, using that chip's assigned slot value. 2. Scan out the multi-cast group address through the TDIB input of all SCANPSC110Fs. Note that this occurs in parallel, resulting in the selection of only those SCANPSC110Fs whose MCGR was previously programmed with the matching multi-cast group code. TABLE 6. Multi-Cast Group Register Addressing MCGR Bits 1, 0 00 01 10 11 3C 3D 3E 3F XX111100 XX111101 XX111110 XX111111 Hex Address Binary Address
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SCANPSC110F
Register Descriptions
Mode Register XXX0X000 XXX0X001 XXX0X010 XXX0X011 XXX0X100 XXX0X101 XXX0X110 XXX0X111 XXX1XXXX
(Continued) TABLE 7. Mode Register Control of LSPN Scan Chain Configuration (If unparked) TDIBRegisterTDOB TDIBRegisterLSP1PADTDOB TDIBRegisterLSP2PADTDOB TDIBRegisterLSP1PADLSP2PADTDOB TDIBRegisterLSP3PADTDOB TDIBRegisterLSP1PADLSP3PADTDOB TDIBRegisterLSP2PADLSP3PADTDOB TDIBRegisterLSP1PADLSP2PADLSP3PADTDOB TDIBRegisterTDOB (Loopback)
X = don't care Register = SCANPSC110F instruction register or any of the SCANPSC110F test data registers PAD = insertion of a 1-bit register for synchronization
Mode Register The mode register is an 8-bit data register used primarily to configure the Local Scan Port Network. The mode register is initialized to "00000001" binary upon entering the TestLogic-Reset state. Bits 0, 1, 2, and 4 are used for scan chain configuration as described in Table 7. When the UNPARK instruction is executed, the scan chain configuration will be as shown in Table 7 above. When all LSPs are parked, the scan chain configuration will be TDIBSCANPSC110F registerTDOB. Bit 3 is used for TCKLn configuration, see Table 8. TABLE 8. Test Clock Configuration Bit 3 1 0 1 0 Parked Parked Unparked Unparked LSPn Stop Run Run Run TCKLn
TABLE 9. Detailed Device Identification (Binary) Bits 31-28 Version 0000 Bits 27-12 Part Number 1111 1100 0000 1110 Bits 11-1 Manufacturer Identity 0000 0001 111 1 Bit 0 1
Linear Feedback Shift Register The SCANPSC110F contains a "signature compactor" which supports test result evaluation in a multi-chain environment. The signature compactor consists of a 16-bit linear-feedback shift register (LFSR) which can monitor localport scan data as it is shifted "upstream" from the SCANPSC110F's local-port network. Once the LFSR is enabled, the LFSR's state changes in a reproducible way as each local-port data bit is shifted in from the local-port network. When all local-port data has been scanned in, the LFSR contains a 16-bit signature value which can be compared against a signature computed for the expected results vector. The LFSR uses the following feedback polynomial: F (x) = X16 + X12 + X3 + X + 1 This signature compactor is used to compress serial data shifted in from the local scan chain, into a 16-bit signature. This signature can then be shifted out for comparison with an expected value. This allows users to test long scan chains in parallel, via Broadcast or Multi-Cast addressing modes, and check only the 16-bit signatures from each module. The LFSR is initialized with a value of "0000" Hex upon reset. 32-Bit TCK Counter Register: The 32-bit TCK counter register enables BIST testing that requires "n" TCK cycles, to be run on a parked LSP while another SCANPSC110F port is being tested. The CNTRSEL instruction can be used to load a count-down value into the counter register via the active scan chain. When the counter is enabled (via the CNTRON instruction), and the LSP is parked, the local TCKs will stop and be held LOW when terminal count is reached. The TCK counter is initialized with a value of "00000000" Hex upon reset.
Bit 3 is normally set to logic "0" so that TCKL is free-running when the local scan ports are parked. When the local ports are parked, bit 3 can be programmed with logic "1", forcing all of the LSP TCKL's to stop. This feature can be used in power sensitive applications to reduce the power consumed by the test circuitry in parts of the system that are not under test. Bit 3 of the mode register must be reset to logic "0" before the UNPARK instruction is executed. Bit 7 is a status bit for the TCK counter. When the counter is on and has reached terminal count (Zero) Bit 7 of the mode register will be high (logic "1"). Bit 7 is read-only and will be LOW in all other conditions. Bits 5 and 6 are reserved for future use. Device Identification Register The device identification register (IDREG) is a 32-bit register compliant with IEEE Std. 1149.1. When the IDCODE instruction is active, the identification register is loaded with the value "0FC0E01F" Hex upon leaving the Capture-DR state (on the rising edge of the TCKB).
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14
SCANPSC110F
Special Features
BIST SUPPORT The sequence of instructions to run BIST testing on a parked SCANPSC110F Bridge port is as follows: 1. Pre-load the Boundary register of the device under test if needed. 2. Initialize the TCK counter to 00000000 Hex. Note that the TCK counter is initialized to 00000000 Hex upon Test-Logic-Reset, so this step may not be necessary. TABLE 10. Reset Configurations for Registers Register MCGR Instruction Mode LFSR 32-Bit Counter Bit Width 2 8 8 16 32 Initial Hex Value 0 AA (IDCODE Instruction) 01 0000 00000000
3. Issue the CNTRON instruction to the SCANPSC110F, to enable the TCK counter. 4. Shift the PARKRTI instruction into the SCANPSC110F instruction register and BIST instruction into the instruction register of the device under test. 5. Issue the CNTRSEL instruction to the SCANPSC110F. 6. Load the TCK counter (Shift the 32-bit value representing the number of TCKL cycles needed to execute the BIST operation into the TCK counter register). 7. Bit 7 of the Mode register can be scanned to check the status of the TCK counter, (MODESEL instruction followed by a Shift-DR). Bit 7 logic "0" means the counter has not reached terminal count, logic "1" means that the counter has reached terminal count and the BIST operation has completed. 8. Execute the CNTROFF instruction. 9. Unpark the LSP and scan out the result of the BIST operation (the CNTROFF instruction must be executed before unparking the LSP). The Self test will begin on the rising edge of TCKB following the Update-DRTAP controller state. RESET Reset operations can be performed at three levels. The highest level resets all SCANPSC110F registers and all of the local scan chains of selected and unselected SCANPSC110Fs. This "Level 1" reset is performed whenever the SCANPSC110F TAP Controller enters the TestLogic-Reset state. Test-Logic-Reset can be entered synchronously by forcing TMSB high for at least five (5) TCKB pulses, or asynchronously by asserting the TRST pin. A "Level 1" reset forces all SCANPSC110Fs into the WaitFor-Address state, parks all local scan chains in the TestLogic-Reset state, and initializes all SCANPSC110F registers.
The SOFTRESET instruction is provided to perform a "Level 2" reset of all LSP's of selected SCANPSC110Fs. SOFTRESET forces all TMSL signals HIGH, placing the corresponding local TAP Controllers in the Test-LogicReset state within five (5) TCKB cycles. The third level of reset is the resetting of individual local ports. An individual LSP can be reset by parking the port in the Test-Logic-Reset state via the PARKTLR instruction. To reset an individual LSP that is parked in one of the other parked states, the LSP must first be unparked via the UNPARK instruction. PORT SYNCHRONIZATION When a LSP is not being accessed, it is placed in one of the four TAP Controller states: Test-Logic-Reset, Run-Test/ Idle, Pause-DR, or Pause-IR. The SCANPSC110F is able to park a local chain by controlling the local Test Mode Select outputs (TMSL(1-3)) (see Figure 4). TMSLn is forced high for parking in the Test-Logic-Reset state, and forced LOW for parking in Run-Test/Idle, Pause-IR, or Pause-DR states. Local chain access is achieved by issuing the UNPARK instruction. The LSPs do not become unparked until the SCANPSC110F TAP Controller is sequenced through a specified synchronization state. Synchronization occurs in the Run-Test/Idle state for LSPs parked in TestLogic-Reset or Run-Test/Idle; and in the Pause-DR or Pause-IR state for ports parked in Pause-DR or Pause-IR, respectively. Figures 11, 12 show the waveforms for synchronization of a local chain that was parked in the Test-Logic-Reset state. Once the UNPARK instruction is received in the instruction register, the LSPC forces TMSL LOW on the falling edge of TCKB.
FIGURE 11. Local Scan Port Synchronization on Second Pass
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SCANPSC110F
Special Features (Continued) This moves the local chain TAP Controllers to the synchronization state (Run-Test/Idle), where they stay until synchronization occurs. If the next state of the SCANPSC110F TAP Controller is Run-Test/Idle, TMSL is connected to TMSB and the local TAP Controllers are synchronized to the SCANPSC110F TAP Controller as shown in Figure 12. If the next state after Update-IR were Select-DR, TMSL would remain LOW and synchronization would not occur until the SCANPSC110F TAP Controller entered the RunTest/Idle state, as shown in Figure 11.
Each local port has its own Local Scan Port Controller. This is necessary because the LSPN can be configured in any one of eight (8) possible combinations. Either one, some, or all of the local ports can be accessed simultaneously. Configuring the LSPN is accomplished with the mode register, in conjunction with the UNPARK instruction. The LSPN can be unparked in one of seven different configurations, as specified by bits 0-2 of the mode register.
Using multiple ports presents not only the task of synchronizing the SCANPSC110F TAP Controller with the TAP Controllers of an individual local port, but also of synchronizing the individual local ports to one another. When multiple local ports are selected for access, it is possible that two ports are parked in different states. This could occur when previous operations accessed the two ports separately and parked them in the two different states. The LSP Controllers handle this situation gracefully. Figure 12 shows the UNPARK instruction being used to access LSP1, LSP2, and LSP3 in series (mode register = "XXX0X111" binary). LSP1 and LSP2 become active as the SCANPSC110F controller is sequenced through the RunTest/Idle state. LSP3 remains parked in the Pause-DR state until the SCANPSC110F TAP Controller is sequenced through the Pause-DR state. At that point, all three local ports are synchronized for access via the active scan chain.
FIGURE 12. Synchronization of the Three Local Scan Ports (LSP1, LSP2, and LSP3)
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SCANPSC110F
Absolute Maximum Ratings(Note 5)
Supply Voltage (VCC) DC Input Diode Current (IIL) VI = -0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current per Output Pin DC Latchup Source or Sink Current Junction Temperature Storage Temperature ESD Last Passing Voltage (Min)
-0.5V to +7.0V -20 mA +20 mA -0.5V to VCC +0.5V -20 mA +20 mA -0.5V to VCC +0.5V 50 mA 50 mA 300 mA +140C -65C to +150C
4000V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate V/t SCAN "F" Series Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 5: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply temperature, and output/input loading variables. Fairchild does not recommended operation of SCAN outside of recommended operation conditions.
4.5V to 5.5V 0V to VCC 0V to VCC
-40C to +85C
125 mV/ns
DC Electrical Characteristics
Symbol VIH VIL VOH (TCKLn, TMSLn, TDOLn) VOH (TCKLn, TMSLn, TDOLn) VOH (TDOB) VOH (TDOB) VOH (TDOB) VOL (TCKLn,TMSLn, TDOLn) VOL (TCKLn,TMSLn, TDOLn) VOL (TDOB) VOL (TDOB) VOL (TDOB) IIN (OE, TCKB,S(0-5)) IIN, MAX (TRST, TDILn, TDIB, TMSB) IIN, MAX (TRST, TDILn, TDIB, TMSB) Parameter Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage Minimum HIGH Output Voltage Minimum HIGH Output Voltage Minimum HIGH Output Voltage Minimum HIGH Output Voltage Maximum LOW Output Voltage Maximum LOW Output Voltage Maximum LOW Output Voltage Maximum LOW Output Voltage Maximum LOW Output Voltage Maximum Input Leakage Current Maximum Input Leakage Current Maximum Input Leakage Current VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 5.5 5.5 5.5 0.001 0.001 TA = 25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 3.15 4.15 2.4 2.4 2.4 2.4 0.1 0.1 0.36 0.36 0.1 0.1 0.55 0.55 0.55 0.55 0.1 2.8 -385 0.55 0.55 1.0 3.6 -385 0.1 0.1 0.44 0.44 0.1 0.1 V TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 3.15 4.15 2.4 2.4 V V V V VOUT = 0.1V or VCC -0.1V VOUT = 0.1V or VCC -0.1V IOUT = -50 A VIN (TDIB, TMSB, TCKB) = VIH IOUT = -24 mA VIN on S(0-5) and TDl(1-3) = VIH, VIL All Outputs Loaded V V V V IOUT = -50 A IOUT = -32 mA All Outputs Loaded IOUT = -24 mA All Outputs Loaded IOUT = +50 A VIN (TDIB, TMSB, TCKB) = VIL IOUT = +24 mA VIN on S(0-5) and TDI(1-3) = VIH, VIL All Outputs Loaded V V V A A A IOUT = +50 A IOUT = +48 mA All Outputs Loaded IOUT = +64 mA All Outputs Loaded VIN = VCC or VIN = GND VIN = VCC VIN = GND Units Conditions
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SCANPSC110F
DC Electrical Characteristics
Symbol IIN, MIN (TDIB, TMSB, TRST, TDILn) ICCT ICCT (TDIB, TMSB, TRST, TDIL) ICC Maximum Quiescent Supply Current ICC, MAX IOLD (TCKLn, TMSLn, TDOLn) IOLD (TDOB) IOHD (TCKLn, TMSLn, TDOLn) IOHD (TDOB) IOZ Maximum Quiescent Supply Current Minimum Dynamic Output Current Minimum Dynamic Output Current Minimum Dynamic Output Current Minimum Dynamic Output Current Maximum 3-STATE Leakage Current IOS (TDOB) Output Short Circuit Current 5.5 Parameter Minimum Input Leakage Current Maximum ICC/Input Maximum ICC/Input VCC (V) 5.5 5.5 5.5
(Continued)
TA = 25C Typ TA = -40C to +85C Guaranteed Limits -160 0.6 0.6 -160 1.5 1.65 A mA mA A VIN = GND VIN = VCC -2.1V VIN = VCC -2.1V Test one at a time with others floating TDIB, TMSB, TRST, TDIL = V CC TDIB, TMSB, TRST, TDIL = GND VOLD = 1.65V max VIN (OE) = V IL (Note 6) VOLD = 0.8V VIN (TRST) = VIH (Note 6) VOHD = 3.85V max (Note 6) VOHD = 2.0V max (Note 6) VIN (OE) = V IH 0.5 5.0 A mA min VIN (TRST) = VIL VO = VCC, GND VO = 0.0V (Note 7)
Units
Conditions
5.5
16
88
5.5 5.5 5.5 5.5 5.5
2.35
2.4 75
mA mA mA mA mA
94
94 -75
-40
-40
5.5
-100
-100
Note 6: Maximum test duration of 2 ms. One output loaded at a time. Note 7: Maximum test duration not to exceed 1 second.
Noise Specifications
Symbol VOLP Parameter Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VOHP Quiet Output Maximum Dynamic VOH VOHV Quiet Output Minimum Dynamic VOH VIHD Minimum HIGH Dynamic Input Voltage Level VILD Maximum LOW Dynamic Input Voltage Level
Note 8: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW. Note 9: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH. Note 10: Maximum number of data inputs (n) switching. (n-1) input switching 0V to 3V. Input under test switching 3V to threshold (V ILD).
VCC (V) 5.0
TA = +25C Type 0.3 0.6
TA = -40C to +85C Guaranteed Limits
Units
Conditions Figure 14
V
(Note 8) Figure 14
5.0
0.3
-0.6
V
(Note 8) Figure 14
5.0
VOH + 0.5
VOH + 1.0
V
(Note 9) Figure 14
5.0
VOH - 0.7
VOH - 1.2
V
(Note 9)
5.5
1.9
2.2
2.2
V
(Note 10)
5.5
1.4
0.8
0.8
V
(Note 10)
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SCANPSC110F
AC Electrical Characteristics
TA = +25C Symbol Parameter VCC (V) Min tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPLH tPZL, tPZH tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPLZ, tPHZ tPLZ, tPHZ Propagation Delay TCKB to TCKLn TCKB to TCKLn Propagation Delay TCKB to TDOLn TCKB to TDOLn Propagation Delay TCKB to TMSLn TCKB to TMSLn Propagation Delay TCKB to TDOB TCKB to TDOB Propagation Delay TMSB to TMSLn Propagation Delay TRST to TMSLn Enable Time TCKB to TDOLn TCKB to TDOLn Disable Time TCKB to TDOLn TCKB to TDOLn Enable Time TCKB to TDOB TCKB to TDOB Disable Time TCKB to TDOB TCKB to TDOB Enable Time OE to TDOLn Disable Time OE to TDOLn Enable Time OE to TMSLn Disable Time OE to TMSLn Enable Time OE to TCKLn Disable Time OE to TCKLn Disable Time TRST to TDOB Disable Time TRST to TDOLn 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 2.0 2.0 3.0 3.0 1.0 1.0 2.0 1.5 1.0 1.0 2.0 1.5 1.0 1.0 2.5 3.0 2.5 1.5 9.0 9.5 10.0 10.0 7.0 8.0 8.0 6.5 5.0 6.0 8.0 6.5 5.0 6.0 11.0 12.0 11.5 11.5 13.0 14.0 15.0 14.0 11.0 13.0 11.5 10.0 9.0 10.0 11.5 10.0 9.0 10.0 16.5 16.5 17.5 17.5 2.0 2.0 3.0 3.0 1.0 1.0 2.0 1.5 1.0 1.0 2.0 1.5 1.0 1.0 2.5 3.0 2.5 1.5 14.5 15.5 17.5 15.0 12.0 13.5 12.5 11.0 10.0 10.5 12.5 11.0 10.0 10.5 18.0 18.0 19.0 19.0 ns ns ns ns ns ns ns ns Figure 16 Figure 16 Figure 16 Figure 16 Figure 16 Figure 16 Figure 15 Figure 15 ns 5.0 4.0 2.5 12.0 9.0 17.0 13.5 4.0 2.5 18.5 14.5 ns 5.0 1.5 2.0 7.5 8.5 12.0 14.0 1.5 2.0 13.5 15.0 ns 5.0 4.0 3.0 12.5 11.0 18.5 15.5 4.0 3.0 20.5 17.0 ns 5.0 5.0 5.0 3.0 2.5 2.5 1.5 4.5 9.5 9.0 8.0 7.5 19.0 14.5 13.5 12.0 12.0 26.5 3.0 2.5 2.5 1.5 4.5 15.5 15.0 13.0 13.0 28.5 ns ns Figure 13 Figure 15 ns Figure 13 5.0 3.5 4.5 15.0 14.5 23.0 21.5 3.5 4.5 25.0 23.0 ns Figure 13 5.0 3.0 3.0 10.0 10.0 14.0 14.5 3.0 3.0 15.0 15.5 ns Figure 13 5.0 3.0 2.5 8.5 8.5 12.5 12.5 3.0 2.5 13.5 13.5 ns Figure 13 CL = 50 pF Typ Max TA = -40C to +85C CL = 50 pF Min Max Units Figure Number
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SCANPSC110F
AC Electrical Characteristics
TA = +25C Symbol Parameter VCC (V) CL = 50 pF Typ tS tH tS tH tS Setup Time TMSB to TCKB Hold Time TMSB to TCKB Setup Time TDIB to TCKB Hold Time TdIB to TCKB Setup Time Sn to TCKB (in Update-DR state) tH Hold Time Sn to TCKB (in Update-DR state) tS Setup Time Sn to TCKB (in Capture-DR or Capture-IR state) tH Hold Time Sn to TCKB (in Capture-DR or Capture-IR state) tS tH tS Setup Time TDILn to TCKB Hold Time TDILn to TCKB Setup Time OE to TCKB (in Capture-DR state) tH Hold Time OE to TCKB (in Capture-DR State) tW tWL tREC tOSHL, tOSLH tOSHL, tOSLH fMAX Clock Pulse Width TCKB (H or L) Clock Pulse Width TRST (L) Recover Time TCKB from TRST Output-to-Output Skew TCKLn Output-to-Output Skew TMSLn (unparked) Maximum Clock Frequency 5.0 5.0 5.0 5.0 5.0 5.0 16.0 6.0 -2.0 20.0 10.0 2.0 1.0 2.0 25 24.0 10.0 2.0 1.0 2.0 ns ns ns ns ns MHz Figure 13 Figure 15 Figure 15 (Note 11) (Note 11) 5.0 0.0 4.0 4.0 ns 5.0 0.0 4.0 4.0 ns 5.0 5.0 -1.5 2.0 2.0 6.0 2.0 6.0 ns ns Figure 13 Figure 13 5.0 1.5 6.0 6.0 ns 5.0 0.0 4.0 4.0 ns 5.0 -3.0 0.0 0.0 ns 5.0 7.5 12.5 12.5 ns 5.0 5.0 5.0 5.0 3.5 -0.5 1.5 1.0 TA = -40C to +85C CL = 50 pF Guaranteed Minimum 8.0 4.0 6.0 4.0 8.0 4.0 6.0 4.0 ns ns ns Figure 13 Figure 13 Figure 13 Units Figure Number
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH). The specification is guaranteed but not tested.
Capacitance
Symbol CIN COUT CPD Parameter Input Pin Capacitance Output Pin Capacitance Power Dissipation Capacitance Typ 5.0 6.5 50 Units pF pF pF VCC is Open VCC is Open VCC = 5.0V Conditions
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SCANPSC110F
AC Waveforms
FIGURE 13. Waveforms for an Unparked SCANPSC110F Bridge in the SHIFT-DR (IR) TAP Controller State
Note A: VOHV and VOLP are measured with respect to ground reference. Note B: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, t f = 3 ns, skew 150 ps.
FIGURE 14. Quiet Output Noise Voltage Waveform
FIGURE 15. Reset Waveforms
FIGURE 16. Output Enable Waveforms
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SCANPSC110F
Appendix
Note: The value of the TMS during the rising edge of TCK is located next to each transition.
FIGURE 17. IEEE 1149.1 TAP Controller State Diagram
Applications Example
FIGURE 18. Boundary Scan Backplane with 10 Card Slots, 8 Slots Are Filled with Boards 1. After the system is powered up a level-1 reset is performed via the TRST input. All TAP Controllers (both SCANPSC110F and local) are asynchronously forced into the Test-Logic-Reset state. All LSP Controllers are in the parked Test-Logic-Reset state; this forces the TMSL outputs of each port to a logic "1", keeping all More Information can be found in Application Notes: board TAPs in the Test-Logic-Reset state. AN-1023 Structural System Test via IEEE Std. 1149.1 The following sequence gives an example of how one might use the SCANPSC110F Bridge to perform 1149.1 operations via a multi-drop scan backplane. The system involved has 10 card slots, 8 of which are filled with modules, and 2 slots are empty. (See Figure 18). with SCANPSC110F Hierarchical and Multidrop Addressable JTAG Port AN-1022 Boundary Scan, An Enabling Technology for System Level Embedded Test 2. The first task of the tester is to find out which slots are occupied on the backplane. This is accomplished by performing a serial poll of each slot address in the system, as assigned by the S0-5 value of each SCANPSC110F in the system.
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SCANPSC110F
Each target slot address is addressed by first sequencing all SCANPSC110Fs on the backplane to the ShiftIR state, and then by shifting in the address of the target slot. The SCANPSC110F TAP controller is then sequenced through the Update-IR state. If a SCANPSC110F with the matching slot identification is present, it is selected. All other SCANPSC110Fs are unselected. To determine whether that slot contains a selected SCANPSC110F, the tester must read back the SCANPSC110Fs S0-5 value (if present). The tester moves the selected SCANPSC110F from the Update-IR state back to the Shift-IR state, and the instruction register is then scanned while loading the next instruction (GOTOWAIT). During the Capture-IR state of the TAP Controller, a "01" pattern is loaded into the two least significant bits of the SCANPSC110F's instruction register, and the most significant six bits capture the value on the S0-5 pins. The captured data is shifted out while the GOTOWAIT command is shifted in. If an "all ones" pattern is returned, a board does not exist at that location. (The "all ones" pattern is caused by the pull-up resistor on the TDI input of the controller, as required for 1149.1 compliance.) At the end of instruction register scan, the GOTOWAIT command is issued and all SCANPSC110F selection controllers enter the Wait-For-Address state. This allows the next SCANPSC110F in the polling sequence to be addressed. The polling process is repeated for every possible board address in the system. In this example, the tester finds that boards #1 through #8 are present, and boards #9 and #10 are missing. Therefore, it will report back its findings and will not attempt to test the missing boards. 3. Infrastructure testing of the populated boards may now proceed. The tester addresses the SCANPSC110F on Board #1 for test operations. SCANPSC110F #1 is now selected, while all others are unselected. Board #1 is wired such that all LSPn's are connected to individual scan chains. The first objective is to test the scan chain integrity of the board. For this task, it is more efficient to configure the LSPN such that all three chains are placed in series. To accomplish this, the MODESEL instruction is issued to place the mode register into the active scan chain, and the binary value "00000111" is shifted into the mode register. The UNPARK instruction is then issued to access all three local chains. Once the UNPARK instruction has been updated and the SCANPSC110F TAP controller is synchronized with the local TAP's, the scan chain integrity test can be performed on the local scan chains. This test is done by performing a Capture-IR and then shifting the scan chain checking the 2 least significant bits of each components instruction register for "01". If the LSB's of any component in the scan chain are not "01", the test fails. Diagnostic software can be used to narrow down the cause of the failure. Next the device identification of each component in the scan chain is checked. This is done by issuing the IDCODE instruction to each component in the scan chain. Components that do not support IDCODE will insert their bypass register into the active scan chain. After the IDCODE register scan, the GOTOWAIT instruction is issued to reset the local scan ports and return the SCANPSC110F Selection controller to the 23
Wait-For-Address state. A sequence similar to step 3 is repeated for each board in the system. 4. Next, the tester addresses Board #1 to perform interconnect testing. For this task, it is efficient to configure the LSPN such that all three chains are placed in series. Therefore, the Mode register should be programmed with the binary value "00000111" (this was done in step 3 above and need not be repeated unless a Test-Logic-Reset was performed since then). The UNPARK instruction is issued to access all three local chains. Once the UNPARK instruction has been loaded and the SCANPSC110F is synchronized with the local TAPs, normal 1149.1 scan operations may commence. To test the interconnect on Board #1, an instruction register scan sequence is performed and the SAMPLE/ PRELOAD instruction is loaded into the instruction register of all target devices. The BYPASS instruction is loaded into the instruction register of SCANPSC110F #1. A data register scan is now performed to preload the first test vector to be applied to the interconnect. 5. After the preload operation is performed, an instruction register scan is used to load the EXTEST instruction into all TAPs (BYPASS loaded into SCANPSC110F #1). The appropriate sequencing is now performed to apply patterns in order to test the interconnect on Board #1. 6. Upon completion of the interconnect test on Board #1, the local chains must be parked. The PARKTLR command is loaded into the instruction register, and the TMSLn outputs of the three local chains are forced HIGH, sending the three local TAPs into the Test-LogicReset state. 7. Now that the Board #1 interconnect has been tested, the interconnect on the other boards in the system must be checked. All SCANPSC110F are returned to the Wait-For-Address state by issuing the GOTOWAlT instruction. Board #2 is addressed next, followed by the rest of the boards in the system. A sequence similar to steps 4 through 6 is used for each board. 8. Assume that boards #6, #7 and #8 are identical, so that it is possible to test them simultaneously. The tester first addresses Board #6. Next the MCGRSEL instruction is issued to place the Multi-Cast Group register into the active scan chain, and the binary value "01" is shifted into the MCGR. The GOTOWAIT instruction is then issued returning all SCANPSC110F's to the WaitFor-Address state. The MCGR for SCANPSC110F #7 and SCANPSC110F #8 are programmed the same as Board #6. Next the Multi-Cast address "00111101" is issued by the tester, which causes the SCANPSC110F Selection controller of SCANPSC110F #6-#8 to enter the Selected-Multi-Cast state. The LFSRON instruction is then issued to enable the signature compaction circuitry on the selected SCANPSC110Fs. The SAMPLE/ PRELOAD and EXTEST instructions are then used to test the interconnects, similar to steps 4 and 5 above. When the test sequence is complete, the GOTOWAIT instruction is issued returning all SCANPSC110Fs to the Wait-For-Address state. SCANPSC110Fs #6, #7, and #8 are then addressed one at a time to read back the test signature from the LFSR (the LFSR is read by selecting it with the LFSRSEL instruction, then scanning out its contents.
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SCANPSC110F
9. After testing the interconnect on the individual boards, the next step is to test the backplane interconnect. This is a pair-wise test between Board #1 and each of the other boards. Board #1 drives test patterns onto the backplane wiring, and the currently addressed slave board senses the written data via its backplane scan interface. In this example, the interconnect between Board #1 and Board #2 is tested first. To test this interconnect, the 1149.1-compliant backplane transceivers, SCAN182245A, SCAN ABT Test Access Logic, on each board must be accessed for scan operations (see Figure 19). For more information on SCAN ABT live insertion capabilities, refer to the SCAN182245A datasheet. First, the system master (Board #1) is addressed and selected. The 1149.1-compliant SCAN ABT transceivers reside on the chain connected to LSP2 on Board #1. The mode register is re-configured so that only port LSP2 is in the chain, and the UNPARK instruction is then used to access this chain. The appropriate instruction register and data register scan sequencing is then performed to apply a pattern to the backplane using the SCAN ABT bus transceiver. 10. To test the backplane interconnect, LSP2 of Board #1 must be parked in the Run-Test/Idle TAP controller state, so that the EXTEST command will stay active when Board #1 is de-selected (the PARKRTI instruction is issued). The GOTOWAIT instruction is then issued to return all boards to the Wait-For-Address state. Each one of the slave boards is then addressed,
one at a time, to sample the backplane signals being driven by Board #1. For example, Board #2 is addressed. The mode register is reconfigured, (if needed), to select the scan chain (LSP2) that includes the SCAN ABT backplane transceivers for Board #2. The UNPARK instruction is issued to unpark LSPn and insert it into the active scan chain. The SAMPLE/PRELOAD instruction is issued to the SCAN ABT backplane transceivers, (BYPASS to other components in the scan chain). The backplane is sampled by sequencing the TAP controller through the Capture-DR state and the data is shifted out and checked by the tester. The PARKRTI instruction is then given to park LSPn of Board #2 in the Run-Test/Idle state, and the GOTOWAIT instruction is issued to return all SCANPSC110Fs to the Wait-For-Address state so that the next board, (Board #3), can be sampled. This procedure is repeated for boards #3-#8, then Board #1 is selected again, a new pattern is shifted out and driven by the EXTEST command, and the slave boards are again sampled. 11. Step 10 is repeated until the backplane interconnect has been sufficiently tested. 12. When testing is complete, the controller sends out the SOFTRESET instruction to all SCANPSC110Fs. This is accomplished by first using the broadcast address, "3B" Hex, to select all SCANPSC110Fs. The SOFTRESET command is then loaded, causing TMSL(1-3) signals to go HIGH; this drives all local TAPs into the TestLogic-Reset state within five TCK cycles.
FIGURE 19. Testing the Backplane Interconnections
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SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide) Package Number M28B
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 25 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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